1. Field of the Invention
This invention relates to a semiconductor memory and a method for conducting a screening test on semiconductor memories. In particular, the present invention relates to means for controlling the operation of reading out data from memory cells as well as to a method for conducting a screening test for detecting defective memory cells of semiconductor memories in the state of wafers.
2. Description of the Related Art
Although the process of manufacturing semiconductor memories is normally held under rigorous control, certain variances are inevitably observed in the quality of manufactured memories, variances, if slight, produced in each manufacturing step are added up until the end of the course of processing wafers and the accumulated variances end up as varied performances of the memory cells contained in the manufactured semiconductor memories.
FIG. 1 of the accompanying drawings shows a frequency curve of variances in the performance of the memory cells contained in the samples of semiconductor memories which were tested after the completion of wafer processing steps.
As seen from FIG. 1, the samples could be divided into three groups. Group (1) represents sound memory cells while group (2) and group (3) respectively represent totally defective memory cells where no data can be written nor read and those that operate only imperfectly although they afford data reading and writing.
Manufacturers of semiconductor memories normally conduct a screening test on wafers to sort out defective ones for the first time in the entire manufacturing process at a test step (so called die sort test step) that comes after the completion of wafer processing steps. In the die sort test step, the tip of the needle of the probe card is brought to contact with the pad of the memory chip formed on each wafer in order to provide the chip with electric power, addresses, input data, control signals and other signals necessary for the chip to operate. Then, the wafer is judged for good or bad by measuring the electric current flowing into the needle and the output data and other data coming from the chip and comparing them with respective reference values.
While the die sort test comprises a number of test items, they are generally grouped into two categories of (1) current test and (2) operation test.
The current test is a test that is carried out first. In this test, the stand-by supply current, the operating supply current and the input pin leakage current will be tested among others for each wafer. When these currents are found within respective specified allowable limits, the chip will be judged as a good one and forwarded to the next test. If it does not meet any of these requirements, however, it is rejected as a defective chip and no further test will be performed on it.
Chips that have passed the current test are then subjected to an operation test. This test is aimed to check if their memory cells afford correct data write-in/read-out operations. The operation test normally comprises a number of test items, including the supply voltage, the voltage and timing of input data, the voltage and timing of address data and the data patterns to be written on the memory cells (the combinations of "0"s and "1"s to be written on the memory cell plane), which are combined in many different ways for data write in/read-out operations to see if the data patterns that have been written in the memory cells can be correctly read out.
With a conventional die sort test, memory cells of group (2) can be efficiently removed from the product. On the other hand, however, it is rather difficult to detect and reject memory cells of group (3) because of the small amount of data to be read out of them (including the difference of the potentials of the bit line pair for voltage read out and the difference of the currents of the bit line pair for current read out).
A variety of screening tests have been proposed and tried to reject memory cells of group (3) at the die sort test step. They may include, among others, a test of operating memory cells with a supply voltage lower (or higher) than the limit values defined in the product specification, a test of operating cells with timing which is more rigorous than the timing defined in the product specification for control signals, addresses and other data and a test where data are given to the memory cell plane in the form of various data patterns (the combinations of "0"s and "1"s of adjacent memory cells).
However, any of the known screen tests is not successful in removing memory cells of group (3). Besides, memory cells of group (3) are instable in performance, meaning that they may some times be identified as defective ones while they may be not in other times if a same test is conducted on them for several times.
The memory cells of group (3) that have not been rejected in the die sort test should be detected in the final test that will be conducted after they are packaged. The semiconductor memories that are identified as defective in the final test inevitably entail wastes of packaging materials and the cost of the test which are by no means negligible.
The problem of being unable to perfectly reject memory cells of group (3) can become very significant in the case of dynamic random access memories (DRAMs) having a large memory capacity and a three dimensional structure of stuck type cells or trench type cells because it is difficult to secure a sufficient cell capacity for such memories and consequently the ratio of defective memories to the total turnout can rise if the stuck type cells and the trench type cells respectively involve imperfect contact of storage nodes and defective trench holes.
Now, the configuration and the operation of a typical conventional DRAM will be described by referring to FIGS. 2 through 5 of the accompanying drawings that partly illustrate the DRAM.
FIG. 2 is a circuit diagram illustrating the configuration of part of the memory cell array MCA of a conventional DRAM and the connection between the memory cell array and the sense amplifiers SA1 through SAn.
In the circuit diagram of the memory cell array MCA, MC, MC, . . . denote respective DRAM cells arranged to form a matrix and WL1 through WLm respectively denote word lines commonly connecting the cells MC, MC, . . . of the respective rows of the matrix, while BL1, /BL1 through BLn, /BLn respectively denote bit lines commonly connecting the cells MC, MC, . . . of the respective columns. DCA denotes a dummy cell section and the dummy cells of this section are connected to the respective bit lines BL1, /BL1 through BLn, /BLn on a one by one basis.
In the dummy cell section DCA of the circuit diagram, DWL and /DWL denote dummy word lines, While VPL and VDC respectively denote the dummy cell capacitor plate potential and the dummy cell writing potential.
The sense amplifiers SA1 through SAn are connected to respective complementary bit line pairs (BL1, /BL1) through (BLn, /BLn) to sense amplify the data read out on the bit lines from memory cell of a selected row.
FIG. 3 is a circuit diagram for one of the memory cells of FIG. 2.
In FIG. 3, Q denotes a MOS transistor for a transfer gate, of which the drain is connected to bit line BLi or /BLi and the gate is connected word line WLi. C denotes a capacitance for storing data having one of its terminals connected to the source of the transistor Q and the other terminal connected to the capacitor plate potential VPL.
FIG. 4 is a circuit diagram for one of the sense amplifiers SA1 through SAn.
In FIG. 4, EQ denotes a bit line precharge equalizing circuit and VPR and /.phi.EQ respectively denote the bit line precharge voltage and a precharge equalizing signal. SN and SP respectively denote an N-channel sense amplifier for sensing the bit line potential and a P-channel sense amplifier for restoring the bit line potential, while /.phi.n and .phi.p respectively denote an N-channel sense amplifier activation signal and a P-channel sense amplifier activation signal.
FIG. 5 is a graph showing voltage waveforms of the DRAM of FIG. 2 typically obtained when it operates to read out data.
In FIG. 5, Vcc denotes the supply voltage and Vcc/2 denotes the bit line precharge potential, while WL, DWL and /DWL respectively denote the word line of the selected row, the selected one of the dummy word lines and the other dummy word line that is not selected. BL and /BL respectively denote one of the bit lines connected to the cells of the selected row and the other bit line which is complementary to the former bit line BL (and connected to the dummy cell DC selected by the dummy word line DWL).
Vn denotes the potential attributable to the coupling noise generated on the former bit line BL through the capacitance between the gate and drain of the cell MC of the selected row when the potential of the word line WL of the selected row rises and Vd denote the potential at tributable to the coupling noise generated on the other bit line /BL connected to the dummy cell DC which is selected as a result of the potential rise in the dummy word line DWL. V1 denote the differential in the signal potential that appears when the "1" data of the selected cell MC is read out on the bit line BL while VO denotes the variation in the signal potential that appears when the "0" data of the selected cell MC is read out on the bit line BL.
As DRAMs are made to have a larger capacity and memory cells are highly miniaturized and integrated to consequently reduce the area that can be spared for cells in each memory device, there arises a remarkable tendency of raised threshold voltage and reduced cell capacitance for "1" data due to the substrate bias effect of the cell transistor, making it difficult to write "1" data in the cell to a sufficient level.
Consequently, the variation .DELTA.vl in the bit line signal potential at the time of reading out "1" data tends to be smaller than the variation .DELTA.vO in the bit line signal potential at the time of reading out "0" data. In other words, the "1" data read out margin (or the sense margin of the bit line sense amplifier) and the "0" data read-out margin come to unbalanced to push up the margin soft error rate of the device.
However, a conventional DRAM cannot arbitrarily change the read-out margins of its memory cells for optimization of the margins.